Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory. Generally, these can be considered either volatile or non-volatile memory.
Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
FIG. 1 illustrates a simplified diagram of a typical NAND flash memory array. The memory array of FIG. 1, for purposes of clarity, does not show all of the elements typically required in a memory array. For example, only two bit lines are shown (BL1 and BL2) when the number of bit lines required actually depends upon the memory density.
The array is comprised of an array of floating gate cells 101 arranged in series strings 104, 105. Each of the floating gate cells 101 are coupled drain to source in each series chain 104, 105. A word line (WL0-WL31) that spans across multiple series strings 104, 105 is coupled to the control gates of every floating gate cell in a row in order to control their operation. The bit lines BL1, BL2 are eventually coupled to sense amplifiers (not shown) that detect the state of each cell. Each series string 104, 105 of floating gate memory cells is coupled to a source line 106 by a source select gate 116, 117 and to an individual bit line (BL1, BL2) by a drain select gate 112, 113. The source select gates 116, 117 are controlled by a source select gate control line SG(S) 118 coupled to their control gates. The drain select gates 112, 113 are controlled by a drain select gate control line SG(D) 114.
Each cell can be programmed as a single bit per cell (i.e., single level cell—SLC) or multiple bits per cell (i.e., multilevel cell—MLC). Each cell's threshold voltage (Vth) determines the data that is stored in the cell. For example, in a single bit per cell, a Vth of 0.5V might indicate a programmed cell while a Vth of −0.5V might indicate an erased cell. The multilevel cell has multiple Vth distributions that each indicates a different state. Multilevel cells take advantage of the analog nature of a traditional flash cell by assigning a bit pattern to a specific voltage range stored on the cell. The distributions are separated by a voltage space or margin that is relatively small due to the limitations of fitting four states into a low voltage memory device.
When programming the above-described cells, they start from an erased state. During the erased state, the non-volatile memory cells draw current. Even after one program pulse, most of the memory cells are not programmed, thus resulting in a “source line bounce” or source line noise where the source line is higher than normal due to the remaining erased cell current usage. When the source line is higher than the body voltage of a memory cell, the threshold voltage for that cell is going to be higher as well. This result of source line bounce is illustrated in FIG. 2.
The left side of FIG. 2 illustrates a program verify operation after one programming pulse. The right side of FIG. 2 illustrates a normal read operation after the programming operation is complete, resulting in a successful verify operation. The left side shows the threshold voltage distribution 200 for a string of memory cells after one programming pulse. During a program verify operation, the memory cells 201 above the verify level are considered to be programmed while the memory cells 202 below the verify level are underprogrammed. During this program verify operation, the source line is substantially higher than normal due to the source line bounce.
The right side of FIG. 2 shows the threshold voltage distribution 210 after the program operation has been completed. This distribution 210 occurs during a normal read operation and shows that most memory cells are now programmed 205 while some are still below the verify level and are read as being under-programmed 203. This is due to the fact that, since the majority of the cells in the string are now programmed, the source line bounce is negligible during the normal read operation. Without the source line bounce, the extra boost to the threshold voltages has been removed and these voltages are now more normal.
The above-mentioned factors can result in overlapping of threshold distributions in memory devices that have a narrow margin between states, such as in MLC devices. Source line bounce or noise can be a factor in SLC memory as well resulting in some memory cells being program verified below the verify level so that they are read as a logical 1 (i.e., erased) instead of a logical 0 (i.e., programmed).
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for tighter control of threshold voltage distributions in memory devices.